PCB Castellated Holes Requirements: Design Rules, Plating and Footprint

Castellated holes are plated through-holes cut in half by the board outline, so a row of half-cylinders of copper runs along the edge. They let a small board, usually a radio, MCU or power module, be soldered flat onto a larger carrier board like a component, with the solder fillet visible from the side. The PCB castellated holes requirements to put on the drawing are the finished hole diameter and pitch, the pad size on top, bottom and inner layers, full plating through the half-hole, a clean routed edge with no copper burrs, and the surface finish. The carrier board then needs a matching footprint and stencil.

What Are Castellations on a PCB?

Half-holes along the edge of a module board that are plated, so each one becomes a solderable terminal on the board’s side. When the module is placed on a carrier, solder flows up the half-cylinder and forms a fillet you can inspect without X-ray. That is the main advantage over a land-grid module, where joints hide underneath.

The Raspberry Pi Pico is a well-documented example: a 51 × 21 mm, 1 mm thick board whose 40 main pins sit on a 2.54 mm pitch with 1 mm holes, made as combined castellated and through-hole pins so it can be soldered flat as a surface-mount module or fitted with headers (Raspberry Pi Pico datasheet). Those are the dimensions of one product, not a general rule, but they show the level of detail a castellated design needs.

How Are Castellated Holes Made?

Full holes are drilled and plated along the future board edge first, and the outline is then routed through their centers. The plated copper must survive that cut. The sequence is usually:

1. Drill holes centered on the outline and plate them with the rest of the board.
2. Pattern and finish the board as normal.
3. Route through the hole centers with tooling and parameters that cut cleanly rather than tearing the copper.
4. Deburr and inspect the edge for copper slivers, lifted plating and torn pads.

Because routing removes half of each barrel, anything that weakens copper adhesion, such as a small pad or thin plating, shows up as pulled or lifted copper on the edge. Many fabricators route castellated edges as a separate step for this reason. The Gerber format identifies these holes with their own attribute, CastellatedDrill, for plated holes cut through by the board edge (Gerber format specification, May 2026); use it, or a separate drill file, so CAM treats them as castellations.

What Design Rules Apply to Castellated Holes?

Center each hole on the outline, give it a generous pad, and keep everything else away from the edge. In practice:

• Hole size and pitch: larger holes are easier to plate and route cleanly and hold more solder; check your fabricator’s minimum hole and pitch for castellations, which is larger than for ordinary vias.
• Pads: put pads on top and bottom layers, and on inner layers where possible, so the barrel is anchored at several points.
• Edge: run castellations only along routed edges, never across a V-score.
• Clearance: keep other copper, traces and planes back from the castellated edge, and do not let mask cover the half-holes.
• Count: a module with very few castellations can tilt or float during reflow; spread them along at least two sides.

IPC-2221C covers plated edges and plated holes in separate clauses (IPC-2221C contents), but its public preview gives no castellation-specific minimum, so the numbers come from the fabricator. For the copper that must stay away from the edge, see the copper-to-edge clearance article.

How Should the Carrier Board Footprint Be Designed?

As a row of pads that extends beyond the module outline, so solder can form a fillet up the half-hole. Make the carrier pads longer than the module’s castellation pads, place them on the same pitch, and take the paste volume from the module maker. Raspberry Pi, for example, publishes a recommended carrier footprint for the Pico and recommends paste zones 163% larger than the footprint.

Keep vias and traces out from under the module where they could short to its bottom-layer copper, and leave room around the edge for inspection and rework. If the module carries a ground pad underneath, plan for venting so flux can escape.

Which Finish and Inspection Suit Castellated Edges?

A flat, solderable finish, most often ENIG, and an edge inspection on every lot. HASL can work but leaves uneven solder in the half-holes, which changes the solder volume at assembly. Whatever the finish, it has to cover the cut barrel as well as the pads.

Check the routed edge under magnification for burrs, copper slivers bridging adjacent half-holes, lifted pads and incomplete plating. IPC-6012F and IPC-A-600M are the acceptance references for plating and visual condition (IPC-6012F contents; IPC-A-600M contents); state the class on the drawing and add a note that castellated edges must be free of burrs and lifted copper.

What Goes on the Castellation Drawing?

Hold the modules in the panel by tabs on edges without castellations, so breaking the panel does not damage the half-holes. Before production, our guide to CAM questions before production lists what the fabricator may ask, and the files a fabrication quote needs covers the rest of the package.

How Can We Help?

QueenEMS makes castellated holes on module boards and checks the castellated edge in DFM review: hole size and pitch against our routing process, pad sizes, copper near the edge and how the module is held in the panel. We drill mechanical holes down to 0.15 mm with ±0.025 mm position accuracy. Send the module Gerbers with the castellations in their own drill file and the carrier footprint if you have it; bare-board pricing follows within 2 hours, along with any DFM questions.

Conclusion

Treat castellations as a defined feature with their own drill data, pads and edge requirements. Contact us with the Gerber files, the castellation detail and quantities. To check a supplier’s capability in general, see our PCB manufacturer capability check, and for shipment records, quality documents before shipment.

FAQ

What are castellations on a PCB? Plated half-holes along a board edge that act as solder terminals, letting a module be soldered flat onto another board.

What are the holes in circuit boards called? Plated through-holes for components and vias, non-plated holes for mounting and tooling, and castellated holes when a plated hole is cut in half at the edge.

Can castellated holes be on a V-scored edge? No. Castellations need a routed edge; a V-score would tear the plating.

Do castellated holes need inner-layer pads? Not always, but pads on inner layers help anchor the plating when the hole is cut.

What finish is best for castellated holes? ENIG is the most common, because it gives flat, solderable half-holes; HASL leaves uneven solder in the edge.