PCB Design for Test: Test Points, ICT and Flying Probe Checklist

Quick Answer: PCB design for test (DFT) means planning how a bare board and an assembled board will be checked before layout is released. Choose the intended test methods with the manufacturer, make required nets accessible, and document what each method can and cannot detect. In-circuit test (ICT) needs a fixture and stable access; flying probe offers more flexibility for changing or smaller builds. Functional test verifies behavior, while boundary scan can help where physical probing is limited. There is no universal test-point spacing, fixture price, or board-count threshold: obtain the actual equipment rules and quote.

Key takeaways

• Define the test objective first: bare-board continuity, assembly defects, programmed behavior and high-speed performance are different checks.
• Ask the chosen manufacturer for its ICT or flying-probe pad, clearance and side-access rules before assigning test points.
• Treat BGA and dense HDI access as a coverage-planning problem; boundary scan and functional test complement physical probing but do not automatically replace it.
• Compare the complete quoted test route, fixture/programming cost, cycle time, expected volume and revision risk instead of applying a generic break-even number.

A board can be manufacturable yet difficult to test. Waiting until routing is frozen may force compromises, but a fixed percentage-complete gate is not a technical requirement. Agree on the test strategy at schematic and placement review, then check actual access again before release.

Which PCB and PCBA tests are you designing for?

The word test covers several stages. Specify the defect or function you need to detect and who owns the program, fixture, limits and failure disposition. A bare-board electrical test does not prove an assembled product works; AOI does not replace an electrical or functional check.

Methods overlap but are not interchangeable. For example, a powered functional test may catch a behavior failure while missing its underlying marginal solder joint. The appropriate combination comes from product risk, accessibility, throughput and the quality plan.

How should you plan test points for ICT and flying probe?

First obtain the test provider’s actual design rules. Altium’s ICT guidance gives example dimensions such as a 1.0 mm preferred pad and roughly 2.5 mm spacing for one fixture context; these are examples, not QueenEMS-wide or universal minimums. Probe head, fixture style, board support, tolerances and assembly keep-outs change what is acceptable. Flying probe also needs physical access, even though it avoids a fixed bed-of-nails fixture.

• Identify power, ground, programming, boundary-scan and critical signal nets required by the proposed test plan; not every net necessarily needs its own physical pad.
• Use named test-point properties and check them against the manufacturer’s rule set, rather than drawing generic exposed copper and assuming it is probeable.
• Confirm pad size, spacing, component height, solder-mask opening, edge clearance, board support and which side can be probed.
• Consider one-sided access when feasible because it can simplify a fixture, but do not claim a fixed saving percentage; routing and coverage still govern.
• Do not use a component pad or via as a test point until the assembler approves contact, solderability, mechanical risk and the resulting coverage.

Altium separates bare-board test-point constraints from assembly-level ICT constraints. Keep those rule sets distinct in the CAD file and share the resulting test-point report with the assembler. A pad that is reachable on the bare board can be blocked by a populated component.

What if a BGA or dense HDI board has little probe access?

Do not declare ICT impossible merely because some nets sit under a BGA. Review accessible fanout, approved vias or pads, boundary-scan-capable devices, power and interface connectors, and a defined functional test. Keysight’s boundary-scan DFT guidance explains how JTAG can test selected interconnects where direct probing is constrained, provided the devices and chain support it. It does not guarantee complete coverage of every net or every failure mode.

Ask the test engineer for a coverage and limitations report: what physical or logical tests will detect, what they will not detect, and how escapes will be controlled. If revision changes are likely, include fixture-change and reprogramming terms in the quote. The PCB assembly testing guide can be used to align test-method vocabulary, but the project-specific test plan must still be agreed in writing.

When does an ICT fixture make economic sense?

The threshold depends on the actual fixture and program charge, per-board test price, cycle time, expected quantity, number of repeats, revision stability and the value of faster fault isolation. A useful comparison is fixture and programming charge + (ICT cost per board × expected boards) versus flying-probe setup/programming charge + (flying-probe cost per board × expected boards). Include debug, repair and repeat-order terms in both offers. This is a decision model, not a published QueenEMS rate card.

If the quoted per-board ICT cost is lower, a simplified break-even quantity is (ICT fixed cost − flying-probe fixed cost) ÷ (flying-probe unit cost − ICT unit cost). The formula has no useful answer if the denominator is zero or negative, the methods have materially different coverage, or a near-term revision will invalidate the fixture. Ask both suppliers to quote the same test scope and acceptance criteria before comparing prices.

A practical DFT review before layout release

Run this review before layout release and repeat it after any change that affects pads, components, connectors or revision-controlled files. To request a build-specific DFT review, send QueenEMS the board files and intended test scope. The company can then confirm its actual process or refer the unresolved access question to the test provider; this page does not claim an undocumented factory capability.

Frequently asked questions

Can flying probe test a board with no dedicated test points?

Sometimes it can contact accessible pads, vias or connectors, but that depends on geometry, population and the provider’s rules. No dedicated pads does not mean guaranteed coverage.

Does boundary scan replace ICT on an HDI board?

Not by itself. It tests only supported devices and interconnects under a valid JTAG design and program. Combine it with physical, inspection and functional methods according to the uncovered risks.

Is one-sided probing always cheaper?

It can simplify fixture design, but actual cost depends on probe density, support, board geometry and required coverage. Request two like-for-like quotes if a dual-sided fixture is being considered.

What should be requested from the assembler before finalizing the PCB?

Ask for its current test-point design rules, target method, access and coverage report, program and fixture responsibilities, test time, reporting format, and a quoted change policy.

Technical sources

• Altium: circuit-board design for in-circuit testers (example fixture-access guidance; confirm against your tester).
• Altium: adding test points (bare-board and assembly test-point constraints).
• Keysight: boundary-scan DFT guidelines (JTAG access in physically constrained designs).

Written by the QueenEMS Engineering Team. Equipment rules, coverage and costs must be confirmed for the actual design and written test plan.