What You Need to Know About PCIe Gen6 PCB Materials

Quick answer: PCIe 6.0 uses 64 GT/s signaling with PAM4, FLIT mode and forward error correction. Its PCB laminate cannot be selected from the generation name alone. Choose the material after modeling the entire channel—including copper, traces, vias, connectors and package—and checking the approved loss and return-loss limits for the actual link. A lower-loss laminate may help, but no one resin grade is universally required or universally disqualified.

What changes with PCIe Gen6?

The PCI-SIG PCIe 6.0 overview states 64 GT/s, PAM4 signaling, FLIT mode and lightweight FEC/CRC. PAM4 carries more information per symbol than NRZ, but the smaller separation between its voltage levels places more pressure on signal integrity. PCI-SIG describes the use of PAM4 to double the rate while maintaining a similar Nyquist frequency to Gen5; it is misleading to claim that the board necessarily operates at a “32 GHz Nyquist frequency.”

Does PCIe Gen6 require a particular PCB material?

No universal laminate list follows from the protocol. Channel reach, component package, connector count, routing, equalization and allowed loss determine whether a candidate construction is sufficient. For example, a short and well-controlled link may permit a different material choice from a long channel with multiple connectors. Do not label I-Tera MT40 a guaranteed failure or Tachyon 100G a guaranteed pass without a modeled and measured channel. The former article’s blanket pass/fail tables and claimed production yields were removed because they lacked the design context needed to substantiate them.

Which material properties matter most?

Compare dielectric Df and Dk at relevant frequencies, but also account for copper-foil profile, dielectric thickness, glass-weave effects, impedance variation and via stubs. The loss budget belongs to the full electrical path, not just a length of bare trace. Use vendor construction-specific data and the fabricator’s finished stackup in the field solver, then review S-parameters and the link simulation with the silicon and connector suppliers. A material with a lower catalog Df can still miss the target if the layout or copper is unfavorable.

Can a hybrid stackup lower material cost?

Sometimes. Putting a lower-loss material only where the critical channel’s fields require it can reduce premium laminate use, but hybrid builds add bonding, CTE and manufacturing constraints. Power and ground planes still participate in return-current and power-integrity behavior; it is inaccurate to say their dielectric properties have “zero electrical impact.” Have the fabricator approve the actual layer sequence and recalculate the channel before quoting a saving. Our PCB materials guide explains the families; it does not replace a channel-specific assessment.

What belongs in a Gen6 PCB review package?

Include the device and connector requirements, topology and maximum trace lengths, stackup proposal, copper foil, target impedance, via structure, loss budget, simulation assumptions and test-coupon plan. Request a fabricator response identifying available laminate constructions and controlled process limits. Send QueenEMS your stackup and channel requirements for a manufacturing review; no material or loss result should be promised before that review.