IPC 2226 HDI type Photorealistic close up of an advanced high density interconnect PCB with glowing microvias and BGA pads

Quick Answer: How to Choose Your HDI Type — Type I has one microvia layer on one or both sides of a core without buried core vias; Type II adds buried core vias while retaining one microvia layer per applicable side. Type III has at least two microvia layers on a side and can use stacked or staggered connections. A conventional 2+N+2 buildup is Type III. Board layer count, BGA pitch, price, and press count do not independently determine the type.

For context on the complete technology, the HDI PCB guide covers how high-density interconnects fit into board design.

Key takeaways:

  • Count the microvia buildup levels and identify the buried connections before selecting Type I, II, or III.
  • Treat the IPC construction type and the product’s performance class as separate specifications.
  • Check a proposed stackup against actual escape routing before committing it to the fabrication drawing.
  • Have quotations identify their manufacturing sequence and included acceptance work; the type label cannot provide those details by itself.

Table of Contents

The useful outcome of choosing an HDI type is an unambiguous construction that can be routed, manufactured, and accepted. Calling a board “Type III” is only the start. The layer connections must explain why that construction is needed and allow a supplier to quote the same board that the design team intends to build.

#1 What Is IPC-2226 and Why Does HDI Type Matter?

IPC-2226 provides design guidance for high-density interconnect printed boards. Its construction categories give designers and fabricators a shared way to describe HDI structures. This article concentrates on Types I, II, and III; they are not the standard’s entire classification system.

The IPC official listing for IPC-2226A identifies Revision A, published in 2017. State the agreed standard revision in project documentation rather than assuming that an unqualified standard number resolves every design or acceptance requirement.

Feature Type I Type II Type III
Microvia buildup One level on one or both sides One level on one or both sides Two or more levels on at least one side
Buried core vias Absent Present Define their use in the specific construction
Typical notation 1+N+1 without buried core vias 1+N+1 with buried core vias 2+N+2, 3+N+3, or another qualifying buildup
What must be specified separately? Dimensions and acceptance requirements Buried-via spans and acceptance requirements All microvia levels, alignment, and acceptance requirements

“Type 0” is sometimes used informally when comparing costs with conventional multilayers. It should not be presented here as an official IPC-2226 HDI category. Describe the comparison board directly: for example, a conventional multilayer using plated through-holes. This avoids confusing a purchasing shorthand with a standard classification.

#2 What Is HDI Type I and When Should You Use It?

Type I is a candidate when one microvia buildup level supplies the needed surface-to-inner-layer access without buried vias inside the core. Through-holes may provide the remaining connections. Its suitability depends on the route, not a prescribed application or maximum total layer count.

In a symmetric 1+N+1 description, the two outer “1” values represent the buildup on each side, and N identifies the underlying layer group. For example, an eight-layer 1+6+1 proposal can use L1–L2 and L8–L7 microvias around a six-layer core. To identify it as Type I, also confirm that the core does not contain buried vias. The notation alone does not settle that distinction.

A useful first check is whether signals entering the first inner routing layer can reach their destinations without another microvia level or an internal buried connection. Review the through-hole lands and antipads as part of that check: their presence can restrict channels even when the initial BGA escape succeeds.

Do not specify exactly two press cycles solely because the drawing says Type I. Ask how the fabricator will construct the core and outer buildup and how the quotation counts those operations. Similarly, via filling and surface requirements must be selected for the actual via function. A via located in a soldering land needs different attention from an otherwise comparable connection outside that land.

#3 What Is HDI Type II and What Designs Actually Need It?

Type II retains one microvia buildup level on each applicable side and introduces buried vias in the core. It becomes relevant when the design needs internal connections that should not continue to the outer board surfaces.

Consider an illustrative eight-layer proposal with outer microvias L1–L2 and L8–L7 and a buried connection spanning L2–L7. That buried path distinguishes it from the Type I example. Show its endpoints and processing requirements in the drawing; the word “buried” does not describe every possible inner-layer span.

The essential Type II versus Type III boundary is the additional microvia buildup level. A path containing separate L1–L2 and L2–L3 microvias has two successive levels on that side. Calling the second microvia “buried” after buildup does not make the board a one-level Type II construction.

Use Type II when its inner connections solve a documented routing problem. It is not mandatory for every 0.5 mm BGA or every six-to-eight-layer board. Conversely, a larger layer count does not automatically require Type III if the needed connections remain within a Type II arrangement. If the need for HDI itself is still uncertain, first review when a conventional multilayer reaches its routing limits.

When comparing a Type II proposal with a Type I alternative, identify which buried connections would disappear and how their nets would be rerouted. Without that route check, a nominal downgrade can leave the design electrically incomplete even though the quotation looks simpler.

#4 What Is HDI Type III and Is the Cost Premium Worth It?

Type III accommodates multiple microvia buildup levels. The extra access is worthwhile when those levels solve a routing requirement that a simpler construction cannot meet within the project’s physical and electrical constraints.

Multiple buildup layers and via alignment

Altium’s 2+N+2 stackup explanation identifies that construction as Type III. The AltiumLive HDI presentation also illustrates 2-N-2 and 3-N-3 Type III arrangements. Neither notation makes a particular production yield or price inevitable.

Multiple microvia levels can be aligned vertically or offset between layers. Both arrangements can remain Type III. Therefore, changing stacked connections to staggered ones is not sufficient evidence that a supplier has reduced the IPC construction type. The drawing must show whether a buildup level has actually been removed.

Where ELIC terminology needs clarification

ELIC describes extensive layer-to-layer interconnection capability and should not be used as a synonym for every Type III board. The IPC framework also includes structures beyond Types I–III. Altium’s ELIC discussion describes sequential buildup and different local via arrangements; a marketing label alone cannot identify the exact core and via architecture.

For an ELIC quotation, request a cross-section showing the available layer-pair connections and the proposed manufacturing sequence. Use those details to establish qualification and compare prices with the other candidate constructions.

#5 How Do the IPC-2226 HDI Types Differ in Lamination Cycles?

Additional buildup levels introduce manufacturing work, but an HDI type is not a complete press schedule. Core construction, sublaminations, and the agreed counting convention affect the reported total.

Altium’s explanation of sequential and sublamination builds shows why the underlying process matters. In a conventional buildup route, buried features are formed while accessible, and subsequent layers cover them. Some internal structures require their own earlier processing. The final type label compresses those details rather than replacing them.

Have the fabricator outline the proposed sequence in order:

  1. Identify the starting core or subassembly and any pre-existing buried connections.
  2. Show each added dielectric and copper buildup, including whether both sides are processed together.
  3. Identify when each blind or buried connection is formed and which filling or surface operations are required.
  4. State which events are counted as lamination cycles in the quotation.

Several holes can be produced during the same stage, while buried structures may require earlier processing. Count the operations in the proposed sequence, including how the quotation treats simultaneous buildup on both sides.

If cost reduction is the objective, find the deepest connection driving an additional buildup level. Removing a few redundant microvias while leaving that connection in place may simplify artwork without eliminating the manufacturing stage responsible for the quoted cost.

#6 What Are the Via Structure Rules for Each HDI Type?

The type identifies the broad construction; the via map supplies the geometry needed to manufacture it. Specify the start and end layers, land dimensions, hole dimensions, permitted placement, and filling requirements for each relevant structure.

Altium’s technical documentation reproduces the IPC-2226A microvia definition, including the 1:1 maximum aspect ratio and 0.25 mm maximum depth. These definition limits do not guarantee that a proposed design lies inside a particular fabricator’s reliable production window. Agree the measurement basis and tolerances, especially when nominal dielectric and finished dimensions differ.

Drawing item Why the type label does not settle it
Layer-pair endpoints Different connections can exist within the same type
Stacked or staggered locations Type III permits more than one arrangement
Hole and land dimensions They depend on the design and supported process
Fill and surface treatment The requirement follows the supporting structure and pad function
Performance specification Construction type is distinct from product acceptance class

In particular, selecting Type III does not establish IPC Class 3 compliance. State the applicable performance requirements separately. A passing visual inspection also does not automatically demonstrate resistance stability under thermal exposure. For the placement decision and its evidence requirements, see stacked versus staggered microvias.

#7 How Does Your HDI Type Choice Affect Cost and Lead Time?

A more demanding construction can increase processing, qualification, and scheduling requirements. The size of that increase must come from a quotation for the actual board. Neither a standard price multiplier nor a fixed number of extra days follows from the Roman numeral.

Compare quotes using a common drawing revision and commercial basis. Material availability, panel utilization, copper requirements, quantity, delivery terms, testing, and one-time setup can change the result. If two suppliers quote different stackups, first establish whether both satisfy the same electrical design before comparing their unit prices.

For an illustrative purchasing review, one supplier lists only the unit price while another separates tooling and coupon testing. Ask for the missing scope rather than assuming the lower number represents the same deliverable. Also distinguish fabrication completion from assembly completion and delivery; these are different dates.

Request the quoted lead time’s starting condition. A schedule beginning after engineering approval cannot be compared directly with one beginning when the RFQ arrives. Ask whether a material substitution, revised via map, or additional qualification would restart that commitment.

Once both quotations cover the same electrical design, compare material availability, setup, fabrication and test milestones. Investigate any remaining price difference against those line items before accepting a change to the construction.

#8 Which HDI Type Fits Your BGA Pitch and Layer Count?

Determine the required connection paths from the package and layout, then classify the resulting stackup. Pitch and total layers help define the routing problem, but they do not provide a complete answer.

Start with the populated ball map

TI’s AM57xx BGA design guidance explains how signal locations and available escape channels affect routing-layer needs. Apply that principle to the selected component’s documentation and the pins used in your circuit. Check whether the first escape layer is enough, whether buried core connections are needed, and whether another microvia buildup level is necessary.

A tightly pitched package with open channels may present a different problem from a fully populated array at the same pitch. Nearby components and plane assignments can further change the available paths. Complete the constrained fanout before treating the type as settled.

Does Moving a Via Change the HDI Type?

Suppose a proposed board uses two outer buildup levels, with L1–L2 microvias aligned above L2–L3 microvias. Moving the lower connections sideways can change the alignment, but two microvia levels remain: this is still Type III.

To evaluate a simpler construction, demonstrate that the nets can use only one outer microvia level. If buried core vias remain, the resulting candidate may be Type II; if they are also eliminated, Type I may be possible. The final classification depends on the complete drawing. This hypothetical comparison establishes no fixed savings, allowable layer limit, or board-area penalty.

#9 How Do You Specify IPC-2226 HDI Type in Your Fabrication RFQ?

Include the type as a concise descriptor alongside the actual construction drawing. The supplier should be able to trace every special via from the manufacturing data to a stated requirement.

What the drawing should contain

Provide the copper-layer order, dielectric stack, microvia drill pairs, buried-via spans, and permitted stacked locations. Identify fill and surface requirements where they affect upper connections or soldering lands. State the intended standard revision and the separate performance specification and class.

For qualification or lot acceptance, define the required evidence rather than requesting an unspecified “IPC test.” IPC-TM-650 2.6.27B covers convection-reflow assembly simulation and describes representative test structures. Identify the agreed method, conditions, acceptance criteria, sampling, and reporting. Set the sample quantity and reporting requirements in the agreed qualification or lot-acceptance plan.

How to settle a conflicting quotation

If the RFQ says Type II while the attached drawing contains two successive buildup microvia levels, resolve the discrepancy before order release. Ask the supplier to identify the contradiction and provide a corrected construction description. Do not let purchasing select whichever label appears less expensive.

The same process applies when CAM proposes replacing an aligned connection with an offset one. Obtain the changed geometry and determine whether it affects routing, electrical behavior, or qualification. Retain the accepted drawing and supplier response together so the production lot can be checked against an identifiable revision.

#10 How Should You Future-Proof Your IPC-2226 HDI Type Selection?

Plan for likely changes by documenting the current construction’s limits and the decisions that would trigger a review. Adding an unused HDI level today does not automatically make tomorrow’s package compatible.

Review package changes at the via map

A replacement component can change ball assignments, supply connections, escape direction, or reference-plane needs even when its pitch appears familiar. Reserved board area may help, but it does not guarantee that a smaller package can be dropped into the existing fanout.

Keep the package version, used-ball map, and required layer access with the design record. When a future revision arrives, compare those inputs before deciding whether the same Type I, II, or III construction remains suitable. Trial-route the changed region rather than carrying forward the old type solely because the board outline is unchanged.

Keep qualification tied to the released construction

Material substitutions and changes to via dimensions or buildup sequence can affect how representative existing qualification remains. Ask engineering and quality to evaluate the changed features against the tested construction. Do not reuse a report just because both versions are called Type III.

For a second source, share the connection requirements and accepted tolerances, then compare its proposed route and evidence with the released design. The objective is reproducible interconnect behavior across approved builds. A common type label is useful for discussion, but the detailed records make that comparison possible.

Conclusion

Choose the IPC-2226 type after establishing the required layer connections. Keep the classification, construction drawing, quotation, and acceptance plan consistent. For HDI PCB fabrication discussions with QueenEMS, send the stackup and via map together with the component information driving the escape requirement.

FAQ

What is the difference between Type II and Type III? Type II has one microvia buildup level on each applicable side plus buried core vias. Type III has multiple microvia buildup levels on at least one side. Counting total board layers is not enough to distinguish them.

Is 2+N+2 Type II? A conventional two-level-per-side buildup is Type III. The number “2” in that notation should not be confused with the Roman numeral II in the construction classification.

Does Type III require stacked microvias? No. Its multiple levels can use staggered connections, stacked connections, or a combination appropriate to the design. Document the actual placement.

Can Type II be changed to Type I? Potentially, if the design eliminates buried core vias while retaining an acceptable one-level microvia buildup. Demonstrate the replacement routing and obtain a revised quotation; no standard savings percentage follows from the label change.

Is ELIC simply another name for Type III? No. ELIC terminology describes broader interconnection capability and requires an explicit architecture. Do not collapse the standard’s additional structures or a supplier’s particular implementation into a generic Type III label.

Written by the QueenEMS Engineering Team.

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