HDI Any-Layer ELIC: When Does Your Board Need It?

Quick Answer: Choose HDI any-layer ELIC when the required connections cannot be routed satisfactorily within a simpler, qualified HDI construction. ELIC is an interconnect architecture that can itself use sequential buildup; it is not the opposite of sequential lamination. Make the decision from a constrained routing study, an actual manufacturing sequence and representative qualification evidence, rather than a fixed BGA pitch or price multiplier.

Any-layer interconnection gives a designer more freedom to connect through the board thickness, but that freedom is valuable only where the layout needs it. A proposal can look attractive in a cross-section and still be unnecessary for the actual ball map, or infeasible on the intended manufacturing route.

This comparison focuses on whether that added interconnect access solves a demonstrated product constraint. It does not classify all HDI types or predict a universal ELIC yield. Those broader structural definitions are covered in the HDI stackup comparison; here the output is a justified construction choice for a particular board.

Table of Contents

• Compare interconnect architectures on the same terms
• Prove the need with a constrained routing study
• Evaluate the manufacturing sequence behind the drawing
• Assess material and interconnect integrity together
• Qualify a source for the actual construction
• Release the chosen interconnect construction explicitly

Compare interconnect architectures on the same terms

Compare an any-layer proposal with a specified alternative, such as a particular 2+N+2 construction. “ELIC versus sequential” is an imprecise comparison because sequential buildup can be part of manufacturing either proposal.

Any-layer does not mean every via is one full-height column

Every-layer interconnect, commonly called ELIC or any-layer HDI, provides interconnection opportunities through successive layers. Copper-filled microvias support dense connections, including stacked arrangements. The available architecture does not require every net to traverse the entire board or every microvia to occupy one continuous vertical column.

Altium’s ELIC manufacturing explanation describes a process starting from an ultra-thin core and adding dielectric and copper-filled microvias sequentially. It also notes that different regions can contain staggered microvias. Consequently, “ELIC has no core” and “staggering is prohibited” are not safe universal definitions.

An actual drawing must show the proposed starting structure and the connections available between layers. A marketing term cannot tell the layout engineer whether a desired transition is allowed, what pad it needs or how it will be formed. Establish those details before assigning the architecture in CAD.

Describe the alternative just as precisely

In 2+N+2 notation, two buildup layers are indicated on each side of a central N-layer portion. Its practical routing capacity depends on the connections provided within that construction. Two proposals with the same notation may differ in buried connections, microvia arrangement or other details relevant to routing.

Keep the total copper layer count, finished thickness, material assumptions and critical electrical requirements visible for both alternatives. Otherwise a comparison may attribute an advantage to ELIC that actually comes from extra layers, finer traces or a different board outline. Those can be legitimate design changes, but they should be evaluated separately.

The right initial question is therefore specific: can this ball map and connection set fit the permitted area and electrical constraints using the candidate construction? An architecture is a means to that result, not a performance rating in itself.

Prove the need with a constrained routing study

Select ELIC because a documented routing constraint requires its interconnection options, not because a device crosses an arbitrary pin-count or pitch threshold. The ball map, power distribution, reference requirements and available channels all affect the answer.

Start with the connections that are hardest to escape

Identify the congested package regions and distinguish signal, power and ground connections. Include permitted via-in-pad structures, pad sizes, trace and space rules, layer transitions, keepouts and the number of usable routing layers. The same nominal package pitch can leave different escape opportunities on different ball maps.

High-speed channels also need their electrical constraints carried into the study. A route that escapes every ball but creates unacceptable discontinuities, reference changes or length relationships has not solved the design problem. Likewise, unrestricted trace narrowing can make a simpler stackup appear feasible while moving the difficulty into manufacturing or signal integrity.

Model the simpler candidate first using rules the proposed fabricator can actually support. Record the remaining unrouted connections and the reason each group is blocked. This produces a useful comparison with an any-layer proposal, rather than a general assertion that “dense devices require ELIC.”

An illustrative routing review

Consider a hypothetical compact board whose central BGA signals cannot reach the required inner routing layers under the proposed 2+N+2 connection map. No performance result or completed customer project is assumed. The team can test several alternatives: revise the escape assignment, add a usable routing layer, change permitted local via arrangements, or evaluate an any-layer structure.

For each alternative, retain the same enclosure and electrical constraints unless the product owner explicitly permits a change. Compare which blocked nets become routable and which new problems appear. An added layer may solve the congestion but exceed thickness limits; a smaller pad may open a channel but violate the qualified fabrication rules. Those outcomes explain why an option is rejected.

If only the any-layer candidate satisfies the combined constraints, that is a defensible reason to proceed to its manufacturing assessment. It is still not proof that the board is ready for production. The fabricator must confirm the proposed structures, and the design team must complete the relevant electrical and mechanical validation.

Keep package interconnect technology distinct from board routing. A processor package containing high-bandwidth memory does not, by itself, establish that all of those package-level connections must be routed on the PCB. Use the actual board-facing interface and package documentation in the escape study.

Evaluate the manufacturing sequence behind the drawing

A manufacturable any-layer proposal needs a defined starting structure and a sequence for adding, drilling and metallizing its connections. Count the operations in that sequence instead of equating the number of dielectric intervals with the number of press cycles.

Simultaneous buildup changes the arithmetic

Under an explicitly assumed symmetric route starting with two copper layers, adding one copper layer to each face per round increases the total by two. Reaching twelve copper layers would then require (12 − 2)/2 = five buildup rounds. This is a construction-counting illustration, not a statement that every twelve-layer ELIC board requires exactly five total press operations.

The total manufacturing route can also include preparation of the starting structure and other operations. The fabricator must explain what its reported count includes. An IPC-hosted manufacturing paper provides a comparable example of a two-layer core followed by four buildup processes for a 4-2-4 structure. See the HDI manufacturing-cost paper.

The important correction is that twelve layers do not automatically mean eleven separate laminations. Two suppliers can even describe an equivalent route with different counts if one includes starting-core manufacture and the other reports only subsequent rounds. Resolve the physical sequence before comparing their estimates.

Inspect the interfaces created at each stage

Map where a new microvia lands on a previously formed feature. The required filling, surface condition and registration depend on that local construction. A process description should identify how the target is prepared and how the resulting interface is assessed, rather than merely listing equipment names.

Hole diameter, capture-pad diameter and annular allowance are distinct quantities. A statement such as “50 µm pad diameter or annular ring” leaves the intended geometry unresolved. Define the actual dimensions and tolerances on the via detail, using the manufacturing convention agreed with the fabricator.

Review any exception against the exact layer pair. Demonstrating one outer microvia does not establish that every internal interface in a dense stack can be made on the same route. Conversely, a route should not be rejected solely because it differs from a generic illustration when the fabricator can provide suitable construction-specific evidence.

Assess material and interconnect integrity together

Material selection, hole preparation and copper-interface quality all contribute to a reliable construction. No single laminate grade, Tg value or aspect ratio proves that an any-layer board will meet its thermal and electrical requirements.

Use named material data and the proposed buildup

Compare the material properties relevant to the application, including electrical behavior, expansion and thermal endurance under the intended conditions. Keep the named material grade and construction with the values. A generic table that assigns one Tg or CTE limit to every ELIC design would conceal differences in methods, reinforcement and manufacturing route.

Fine routing can also make copper geometry and the selected material system important to electrical performance. Evaluate these together with the actual stackup and fabricator rules. Do not prescribe a material solely because it is described as low loss or high Tg; those descriptions do not confirm the full buildup process or finished interconnect quality.

When a supplier proposes an equivalent material, review what changes in the stackup and process. An electrical substitution can alter pressed thickness or other manufacturing assumptions. The design team should know whether its via geometry, impedance calculations or qualification evidence needs reassessment.

Geometry acceptance is not thermal qualification

An aspect-ratio calculation is one part of the dimensional review. Use the microvia depth-and-diameter calculation for its measurement conventions and tolerance treatment. Even a dimensionally acceptable segment can contain an interface whose performance requires separate evaluation.

IPC’s 2019 microvia warning described latent failures appearing after conventional acceptance. It supports testing representative structures and considering the limits of inspection; it does not support a universal equation relating board life inversely to lamination count.

For an any-layer proposal, ask how the qualification specimen represents the relevant stacked and offset connections. Match the test conditions to the product and assembly requirements. Do not assume that a successful coupon from a simpler construction demonstrates every interface in the proposed board, or that an added cycle necessarily reduces service life by a calculable amount.

Qualify a source for the actual construction

Evaluate the supplier’s ability to deliver the proposed board at the intended quantity and acceptance level. Neither a list of machines nor a claim to offer “advanced HDI” establishes production capability for the chosen architecture.

Request representative evidence

The supplier should identify the manufacturing location and proposed route, then explain the relevance of its dimensional and performance evidence. Ask whether the demonstrated material, microvia geometry, buildup arrangement and test conditions represent the new design. Differences do not automatically invalidate earlier data, but their applicability needs an engineering explanation.

A capability statement should distinguish routine production, a qualified exception and a development trial. Those categories have different implications for tooling commitments, first-article quantities and schedule. Treat an untested extension of capability as development work rather than pricing it as a stable repeat-production route.

There is no need to assert that only a fixed number of factories worldwide can manufacture ELIC. Such a count changes and depends on what level of production and qualification is being counted. It is more useful to establish what the specific candidate can demonstrate for the requested construction.

Define yield before comparing percentages

If production data are available, establish their denominator and process stage. First-pass accepted panels, individual boards after rework and final shipment results are different measures. The time period, product mix and rejection criteria also affect the comparison. A percentage averaged across unrelated jobs cannot predict the result of the new board.

Separate manufacturing yield from field reliability. A factory can deliver accepted boards after screening or rework without that shipment percentage demonstrating long-term performance. Conversely, a qualification result on representative samples does not establish the factory’s expected recurring cost or capacity.

Obtain quotations for the feasible alternatives using the same quantity, acceptance scope and delivery assumptions. ELIC may involve additional processing or capability constraints, but the size of a premium must come from the actual quotes. Use the sequential-lamination cost comparison to normalize recurring prices, setup and counting conventions without inventing fixed multipliers.

Release the chosen interconnect construction explicitly

The released package should define the interconnections that solved the routing problem and the fabrication assumptions under which they were accepted. “ELIC approved” is too broad to prevent a later substitution that changes those assumptions.

Include the final layer stack, a via layer-pair map, the relevant local cross-sections and the geometry used in the routing study. Show which microvias are stacked or offset and where they land on filled or other underlying structures. Keep material, copper and dimensional requirements tied to the same revision as the electrical layout.

The supplier’s manufacturing response should identify any departures from that package. If a different starting structure or via arrangement is proposed, the designer needs to know whether the available layer transitions have changed. A drawing that still carries the same total layer count can nonetheless require another escape-routing or electrical review.

Release question	Information needed to answer it
Why is any-layer access needed?	Documented routing constraint and comparison with feasible alternatives
What exactly will be fabricated?	Stackup, layer-pair connections and local via details
Which capability has been demonstrated?	Relevant construction and qualification evidence
What is included in the commercial offer?	Quantity, route assumptions, setup, testing and delivery basis
Which changes reopen the decision?	Material, geometry, connection or manufacturing-route departures

For first articles, agree which measurements and tests will confirm the new construction before committing the remaining quantity. The plan should connect those checks to the risks identified during route review. Avoid an undifferentiated instruction to “inspect everything” that does not identify how a critical internal interface will be assessed.

Keep the rejected alternatives and their actual limitations in the design record. This is useful when a later component change, board-size allowance or manufacturing constraint reopens the architecture choice. A previously unnecessary any-layer route can become justified, or a simplified construction can become feasible, when the underlying constraints change.

For a QueenEMS review of an any-layer proposal, provide the candidate interconnect drawing, the constrained package region and the requirement that prevents the simpler route from working. Include the intended build quantities and qualification needs. That supports a discussion of feasible fabrication options and their quotation basis without treating ELIC as a default upgrade.

FAQ

Does a fine-pitch BGA always require ELIC?

No. Pitch alone does not define escape feasibility. The ball map, available routing layers, geometry rules and product constraints determine whether a simpler construction can work.

Can an any-layer board contain staggered microvias?

Yes. An any-layer architecture does not require every connection to form one vertical column. Confirm the permitted arrangements and their qualification in the specific manufacturing proposal.

Is a twelve-layer ELIC board always eleven press cycles?

No. Layer intervals are not press-cycle counts. Identify the starting structure, simultaneous buildup sequence and treatment of earlier core operations before stating a total.

Written by the QueenEMS Engineering Team